The switch originally was designed to have high-speed HSTL point-to-point connections between port cards and fabrics running at 250 MHz. This was proven to be too fast and signal integrity could not be guaranteed due to the long trace length that exist. A more robust method had to be devised. The new method uses a network of gigabit transceivers between port cards and fabrics. The gigabit network is comprised of gigabit transmitters and receivers that communicate with each other at up to 1.3 GHz. The interfaces to each transceiver are an 8-bit data bus running at 125 MHz. Since the frequency of operation was reduced by half, the bus widths had to be multiplied by two. This new method provides to be more robust and has better noise rejection since the gigabit transceivers use differential pairs to communicate with each other. Since these gigabit transceivers are replacing point-to-point buses and some buses are larger than 8 bits wide, multiple gigabit transceivers need to be used to make up these buses. The initial total number of gigabit transceivers required was as follows: 22 transmitters per Striper, 40 receivers per Aggregator, 52 transmitters per Separator and 28 receivers per Unstriper. For a 480 G switch, this would total to about (48 port cards)(4Stripers)(22)+(13 fabrics)(9 Aggregators)(40)+(13 fabrics)(9 Separators)(52)+(48 port cards)(4 Unstripers)(28)=4224+4680+6084+376=20364. This large number of gigabit transceivers proved to consume too much power and take up too much boards space. At an average of 0.29 Watts of power dissipation per transceiver, the total power dissipation would have been 5,905 Watts (20364)(0.029).
The present invention using the gigabit transceivers solves the following problems:    1. Reduces the total number of gigabit transceivers required.    2. Reduces total power requirements of whole system.    3. Reduces board space requirements.    4. Handles un-synchronized updates to gigabit network.    5. Minimizes I/O requirements on backplane connectors.    6. Reduces PCB trace routing complexity.    7. Maximizes symmetry between ASICs which will simplify unique mux/demux structures required.
This optimization solves all the above problems by intelligently allocating gigabit transceivers to be re-used in modes where they can be re-used. This technique allows changes in the configuration of the switch (40 G, 80 G, 120 G, etc.) To alter the gigabit transmitter and receiver assignment to be un-synchronized as long as the switch configuration is changed up or down by one step in the configuration.
A switch which stripes data onto multiple fabrics and sends parity data to another fabric has been described in U.S. patent application Ser. No. 09/333,450, incorporated by reference herein. See also U.S. patent application Ser. No. 09/293,563 which describes a wide memory TDM switching system, incorporated by reference herein.